Conventional memory architectures which use a common memory shared by multiple input/output devices, including central processing units (CPU's), which require random access of the memory, generally provide insufficient memory bandwidth to allow each device to communicate, and hence to operate, at peak performance. This condition occurs because the bandwidth available for communicating with the memory must be divided among the various input/output devices and processors to allow each device to access the memory. The memory, having a peak operating throughput, simply cannot communicate fast enough, that is, it does not have a high enough communications bandwidth to allow all of the devices connected to it to perform at their maximum rated specifications.
The traditional solutions to this problem have been many and include, for example, memory caching wherein each input/output device and/or CPU is provided with cache memory for data or instructions, interleaving the memories, bank switched memories, the use of a page mode or static column access memory, the use of time-sharing or time-slicing techniques to provide access to the common memory; and the use of separate buffer memories for use by the input/output devices as an intermediate storage. Each of these solutions has always required various forms of data and address path sharing and address generation by the central processing unit (CPU) of the apparatus. In addition, all of the methods require contention resolution or arbitration between devices vying for use of the memory element.
In a typical example, a digital controller system can require an estimated peak memory bandwidth of 30 megabytes per second. The requirement may be distributed between (a) a processor which can transfer data, in the burst mode, at 20 megabytes per second, (b) two independent disk drive input/output devices which have a peak data rate of 3 megabytes per second per port, and (c) an 8 megahertz 80286 microprocessor which requires an estimated bandwidth on the order of 4 megabytes per second, assuming no wait states and/or continuous program execution. Such overal memory bandwidth requirements are beyond that available by typical dynamic or static random access memories (RAM's).
It is therefore, an object of the invention to provide high bandwidth in a shared memory environment which allows high performance CPU's and high performance input/output (I/O) devices to operate with a shared memory while maintaining high operating performance. Other objects of the invention are a method and apparatus for increasing performance of a digital processing system, for providing improved data transmission between auxiliary devices and the shared memory, for improving access by a central processing unit to a shared memory, for reducing the overall cost and increasing the reliability of a shared memory digital processing system, and reducing contention and priority problems in a high performance digital processing system.